Electrostatic discharge is a major source of failure in integrated circuits. Unless appropriate measures are taken to prevent it, an electrostatic charge can build up on an integrated circuit (IC) that has sufficient energy to destroy part of the IC during its discharge. A detailed discussion of ESD is found in A. Amerasekera et al., ESD in Silicon Integrated Circuits, 2d ed., Wiley 2002, which is incorporated herein by reference.
FIG. 1 illustrates a conventional ESD protection circuit 100 for high speed input/output circuits for an integrated circuit. Circuit 100 comprises an input/output pad 110 connected to an input/output lead 120, a ground lead 130, a silicon controlled rectifier (SCR) 140 connecting the input/output lead 120 and ground lead 130, and a trigger device 150. The circuits to be protected are schematically represented by block 160. When an over voltage condition is detected on input/output lead 120, SCR 140 turns on to discharge the voltage to ground, thereby protecting the circuits 160 from the over voltage. Circuits such as that of FIG. 1 are disclosed, for example in Mergens et al., U.S. Pat. No. 6,803,633, which is incorporated herein by reference.
Unfortunately, the turn on time of an SCR is relatively long while certain electrostatic discharge phenomena are quite fast. For example, electrostatic discharges associated with manufacturing and chip handling equipment tend to be extremely fast, high voltage pulses. This type of phenomena, which is referred to under the terms Charged Device Model (CDM) and Field Induced Charged Device Model (FCDM), is described in greater detail at pages 12-14 and 28-40 of ESD in Silicon Integrated Circuits, which is incorporated herein by reference. Because SCRs are relatively slow, SCRs are barely meeting the requirements for CDM tests in some modern process technologies.